LPC1752 Pin function table.

Pin Symbol Pinsel
reg
Pin
sel
ix
I/O Pin
Function
Function
Block
Description
1 TDO/SWO O TDO JTAG Test Data out for JTAG interface.
O SWO SWDEBUG Serial wire trace output.
2 TDI I TDI JTAG Test Data in for JTAG interface.
3 TMS/SWDIO I TMS JTAG Test Mode Select for JTAG interface.
I SWDIO SWDEBUG Serial wire debug data input/output.
4 !TRST I !TRST JTAG Test Reset for JTAG interface.
5 TCK/SWDCLK I TCK JTAG Test Clock for JTAG interface.
I SWDCLK SWDEBUG Serial wire clock.
6 P0.26/AD0.3/RXD3 pinsel1
21:20
x
0 I/O P0.26 GPIO 0 General purpose digital input/output pin. When configured as an ADC input or DAC output, the digital section of the pad is disabled.
1 I AD0.3 ADC A/D converter 0, input 3.
3 I RXD3 UART 3 Receiver input for UART3.
7 P0.25/AD0.2/TXD3 pinsel1
19:18
x
0 I/O P0.25 GPIO 0 General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled.
1 I AD0.2 ADC A/D converter 0, input 2.
3 O TXD3 UART 3 Transmitter output for UART3.
8 VDDA P VDDA ADC analog 3.3 V pad supply voltage: This can be connected to the same supply as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. Note: this pin should be tied to 3.3v if the ADC and DAC are not used.
9 VSSA P VSSA ADC analog ground: 0 V reference. This should be the same voltage as VSS, but should be isolated to minimize noise and error.
10 VREFP I VREFP ADC ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. The voltage level on this pin is used as a reference for ADC and DAC.
Note: this pin should be tied to 3.3v if the ADC and DAC are not used.
11 !RSTOUT O !RSTOUT Main This is a 3.3 V pin. A LOW on this pin indicates that the LPC17xx is in a Reset state.
12 VREFN I VREFN ADC ADC negative reference voltage: This should be the same voltage as VSS but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC.
13 RTCX1 I RTCX1 RTC Input to the RTC oscillator circuit.
14 !RESET I !RESET Main External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. This is a 5 V tolerant pad with a 20 ns glitch filter, TTL levels and hysteresis.
15 RTCX2 O RTCX2 RTC Output from the RTC oscillator circuit.
16 VBAT I VBAT RTC RTC domain power supply: 3.3 V on this pin supplies the power to the RTC peripheral.
17 P1.31/SCK1/AD0.5 pinsel3
31:30
x
0 I/O P1.31 GPIO 1 General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled.
2 I/O SCK1 SSP 1 Serial Clock for SSP1.
3 I AD0.5 ADC A/D converter 0, input 5.
18 P1.30/VBUS/AD0.4 pinsel3
29:28
x
0 I/O P1.30 GPIO 1 General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled.
2 I VBUS USB-Device Monitors the presence of USB bus power. Note: This signal must be HIGH for USB reset to occur.
3 I AD0.4 ADC A/D converter 0, input 4.
19 XTAL1 I XTAL1 Main Input to the oscillator circuit and internal clock generator circuits.
20 XTAL2 O XTAL2 Main Output from the oscillator amplifier.
21 VDD(3V3) I VDD(3V3) Main 3.3 V supply voltage: This is the power supply voltage for I/O other than pins in the Vbat domain.
22 P0.29/USB_D+ pinsel1
27:26
x
0 I/O P0.29 GPIO 0 General purpose digital input/output pin. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only).
1 I/O USB_D+ USB-Device USB bidirectional D+ line.
23 P0.30/USB_D- pinsel1
29:28
x
0 I/O P0.30 GPIO 0 General purpose digital input/output pin. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only).
1 I/O USB_D- USB-Device USB bidirectional D- line.
24 VSS I VSS Main ground: 0 V reference.
25 P1.18/USB_UP_LED/PWM1.1/CAP1.0 pinsel3
5:4
x
0 I/O P1.18 GPIO 1 General purpose digital input/output pin.
1 O USB_UP_LED USB-Device USB GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend.
2 O PWM1.1 PWM Pulse Width Modulator 1, channel 1 output.
3 I CAP1.0 Timer 1 Capture input for Timer 1, channel 0.
26 P1.19/MCOA0/CAP1.1 pinsel3
7:6
x
0 I/O P1.19 GPIO 1 General purpose digital input/output pin.
1 O MCOA0 Motor-PWM Motor control PWM channel 0, output A.
3 I CAP1.1 Timer 1 Capture input for Timer 1, channel 1.
27 P1.20/MCI0/PWM1.2/SCK0 pinsel3
9:8
x
0 I/O P1.20 GPIO 1 General purpose digital input/output pin.
1 I MCI0 Motor-PWM Motor control PWM channel 0 input. Also Quadrature Encoder Interface PHA input.
2 O PWM1.2 PWM Pulse Width Modulator 1, channel 2 output.
3 I/O SCK0 SSP 0 Serial clock for SSP0.
28 P1.22/MCOB0/MAT1.0 pinsel3
13:12
x
0 I/O P1.22 GPIO 1 General purpose digital input/output pin.
1 O MCOB0 Motor-PWM Motor control PWM channel 0, output B.
3 O MAT1.0 Timer 1 Match output for Timer 1, channel 0.
29 P1.23/MCI1/PWM1.4/MISO0 pinsel3
15:14
x
0 I/O P1.23 GPIO 1 General purpose digital input/output pin.
1 I MCI1 Motor-PWM Motor control PWM channel 1 input. Also Quadrature Encoder Interface PHB input.
2 O PWM1.4 PWM Pulse Width Modulator 1, channel 4 output.
3 I/O MISO0 SSP 0 Master In Slave Out for SSP0.
30 P1.24/MCI2/PWM1.5/MOSI0 pinsel3
17:16
x
0 I/O P1.24 GPIO 1 General purpose digital input/output pin.
1 I MCI2 Motor-PWM Motor control PWM channel 2 input. Also Quadrature Encoder Interface INDEX input.
2 O PWM1.5 PWM Pulse Width Modulator 1, channel 5 output.
3 I/O MOSI0 SSP 0 Master Out Slave In for SSP0.
31 P1.25/MCOA1/MAT1.1 pinsel3
19:18
x
0 I/O P1.25 GPIO 1 General purpose digital input/output pin.
1 O MCOA1 Motor-PWM Motor control PWM channel 1, output A.
3 O MAT1.1 Timer 1 Match output for Timer 1, channel 1.
32 P1.26/MCOB1/PWM1.6/CAP0.0 pinsel3
21:20
x
0 I/O P1.26 GPIO 1 General purpose digital input/output pin.
1 O MCOB1 Motor-PWM Motor control PWM channel 1, output B.
2 O PWM1.6 PWM Pulse Width Modulator 1, channel 6 output.
3 I CAP0.0 Timer 0 Capture input for Timer 0, channel 0.
33 VSS I VSS Main ground: 0 V reference.
34 VDD(REG)(3V3) I VDD(REG)(3V3) Main 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip voltage regulator only.
35 P1.28/MCOA2/PCAP1.0/MAT0.0 pinsel3
25:24
x
0 I/O P1.28 GPIO 1 General purpose digital input/output pin.
1 O MCOA2 Motor-PWM Motor control PWM channel 2, output A.
2 I PCAP1.0 PWM Capture input for PWM1, channel 0.
3 O MAT0.0 Timer 0 Match output for Timer 0, channel 0.
36 P1.29/MCOB2/PCAP1.1/MAT0.1 pinsel3
27:26
x
0 I/O P1.29 GPIO 1 General purpose digital input/output pin.
1 O MCOB2 Motor-PWM Motor control PWM channel 2, output B.
2 I PCAP1.1 PWM Capture input for PWM1, channel 1.
3 O MAT0.1 Timer 0 Match output for Timer 0, channel 1.
37 P0.0/RD1/TXD3/SDA1 pinsel0
1:0
x
0 I/O P0.0 GPIO 0 General purpose digital input/output pin.
1 I RD1 CAN CAN1 receiver input.
2 O TXD3 UART 3 Transmitter output for UART3.
3 I/O SDA1 I2C 1 I2C1 data input/output (this pin is not fully compliant with the I2C-bus specification, see Section 19–4 for details).
38 P0.1/TD1/RXD3/SCL1 pinsel0
3:2
x
0 I/O P0.1 GPIO 0 General purpose digital input/output pin.
1 O TD1 CAN CAN1 transmitter output.
2 I RXD3 UART 3 Receiver input for UART3.
3 I/O SCL1 I2C 1 I2C1 clock input/output (this pin is not fully compliant with the I2C-bus specification, see Section 19–4 for details).
39 P0.10/TXD2/SDA2/MAT3.0 pinsel0
21:20
x
0 I/O P0.10 GPIO 0 General purpose digital input/output pin.
1 O TXD2 UART 2 Transmitter output for UART2.
2 I/O SDA2 I2C 2 I2C2 data input/output (this is not an open-drain pin).
3 O MAT3.0 Timer 3 Match output for Timer 3, channel 0.
40 P0.11/RXD2/SCL2/MAT3.1 pinsel0
23:22
x
0 I/O P0.11 GPIO 0 General purpose digital input/output pin.
1 I RXD2 UART 2 Receiver input for UART2.
2 I/O SCL2 I2C 2 I2C2 clock input/output (this is not an open-drain pin).
3 O MAT3.1 Timer 3 Match output for Timer 3, channel 1.
41 P2.10/!EINT0/NMI pinsel4
21:20
x
0 I/O P2.10 GPIO 2 General purpose digital input/output pin. 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. Note: A LOW on this pin while !RESET is LOW forces the on-chip bootloader to take over control of the part after a reset and go into ISP mode. See Section 32–1.
1 I !EINT0 Main External interrupt 0 input.
2 I NMI Main Non-maskable interrupt input.
42 VDD(3V3) I VDD(3V3) Main 3.3 V supply voltage: This is the power supply voltage for I/O other than pins in the Vbat domain.
43 VSS I VSS Main ground: 0 V reference.
44 P0.22/RTS1/TD1 pinsel1
13:12
x
0 I/O P0.22 GPIO 0 General purpose digital input/output pin.
1 O RTS1 UART 1 Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal.
3 O TD1 CAN CAN1 transmitter output.
45 P0.18/DCD1/MOSI0/MOSI pinsel1
5:4
x
0 I/O P0.18 GPIO 0 General purpose digital input/output pin.
1 I DCD1 UART 1 Data Carrier Detect input for UART1.
2 I/O MOSI0 SSP 0 Master Out Slave In for SSP0.
3 I/O MOSI SPI Master Out Slave In for SPI.
46 P0.17/CTS1/MISO0/MISO pinsel1
3:2
x
0 I/O P0.17 GPIO 0 General purpose digital input/output pin.
1 I CTS1 UART 1 Clear to Send input for UART1.
2 I/O MISO0 SSP 0 Master In Slave Out for SSP0.
3 I/O MISO SPI Master In Slave Out for SPI.
47 P0.15/TXD1/SCK0/SCK pinsel0
31:30
x
0 I/O P0.15 GPIO 0 General purpose digital input/output pin.
1 O TXD1 UART 1 Transmitter output for UART1.
2 I/O SCK0 SSP 0 Serial clock for SSP0.
3 I/O SCK SPI Serial clock for SPI.
48 P0.16/RXD1/SSEL0/SSEL pinsel1
1:0
x
0 I/O P0.16 GPIO 0 General purpose digital input/output pin.
1 I RXD1 UART 1 Receiver input for UART1.
2 I/O SSEL0 SSP 0 Slave Select for SSP0.
3 I SSEL SPI Slave Select for SPI.
49 P2.9/USB_CONNECT/RXD2 pinsel4
19:18
x
0 I/O P2.9 GPIO 2 General purpose digital input/output pin.
1 O USB_CONNECT USB-Device Signal used to switch an external 1.5 kΩ resistor under software control. Used with the SoftConnect USB feature.
2 I RXD2 UART 2 Receiver input for UART2.
50 P2.8/TXD2 pinsel4
17:16
x
0 I/O P2.8 GPIO 2 General purpose digital input/output pin.
2 O TXD2 UART 2 Transmitter output for UART2.
51 P2.7/RTS1 pinsel4
15:14
x
0 I/O P2.7 GPIO 2 General purpose digital input/output pin.
2 O RTS1 UART 1 Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal.
52 P2.6/PCAP1.0/RI1/TRACECLK pinsel4
13:12
x
0 I/O P2.6 GPIO 2 General purpose digital input/output pin.
1 I PCAP1.0 PWM Capture input for PWM1, channel 0.
2 I RI1 UART 1 Ring Indicator input for UART1.
3 I TRACECLK Trace Trace Clock.
53 P2.5/PWM1.6/DTR1/TRACEDATA0 pinsel4
11:10
x
0 I/O P2.5 GPIO 2 General purpose digital input/output pin.
1 O PWM1.6 PWM Pulse Width Modulator 1, channel 6 output.
2 O DTR1 UART 1 Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal.
3 O TRACEDATA0 Trace Trace data, bit 0.
54 P2.4/PWM1.5/DSR1/TRACEDATA1 pinsel4
9:8
x
0 I/O P2.4 GPIO 2 General purpose digital input/output pin.
1 O PWM1.5 PWM Pulse Width Modulator 1, channel 5 output.
2 I DSR1 UART 1 Data Set Ready input for UART1.
3 O TRACEDATA1 Trace Trace data, bit 1.
55 P2.3/PWM1.4/DCD1/TRACEDATA2 pinsel4
7:6
x
0 I/O P2.3 GPIO 2 General purpose digital input/output pin.
1 O PWM1.4 PWM Pulse Width Modulator 1, channel 4 output.
2 I DCD1 UART 1 Data Carrier Detect input for UART1.
3 O TRACEDATA2 Trace Trace data, bit 2.
56 VDD(3V3) I VDD(3V3) Main 3.3 V supply voltage: This is the power supply voltage for I/O other than pins in the Vbat domain.
57 VSS I VSS Main ground: 0 V reference.
58 P2.2/PWM1.3/CTS1/TRACEDATA3 pinsel4
5:4
x
0 I/O P2.2 GPIO 2 General purpose digital input/output pin.
1 O PWM1.3 PWM Pulse Width Modulator 1, channel 3 output.
2 I CTS1 UART 1 Clear to Send input for UART1.
3 O TRACEDATA3 Trace Trace data, bit 3.
59 P2.1/PWM1.2/RXD1 pinsel4
3:2
x
0 I/O P2.1 GPIO 2 General purpose digital input/output pin.
1 O PWM1.2 PWM Pulse Width Modulator 1, channel 2 output.
2 I RXD1 UART 1 Receiver input for UART1.
60 P2.0/PWM1.1/TXD1 pinsel4
1:0
x
0 I/O P2.0 GPIO 2 General purpose digital input/output pin.
1 O PWM1.1 PWM Pulse Width Modulator 1, channel 1 output.
2 O TXD1 UART 1 Transmitter output for UART1.
61 P0.9/MOSI1/MAT2.3 pinsel0
19:18
x
0 I/O P0.9 GPIO 0 General purpose digital input/output pin.
2 I/O MOSI1 SSP 1 Master Out Slave In for SSP1.
3 O MAT2.3 Timer 2 Match output for Timer 2, channel 3.
62 P0.8/MISO1/MAT2.2 pinsel0
17:16
x
0 I/O P0.8 GPIO 0 General purpose digital input/output pin.
2 I/O MISO1 SSP 1 Master In Slave Out for SSP1.
3 O MAT2.2 Timer 2 Match output for Timer 2, channel 2.
63 P0.7/SCK1/MAT2.1 pinsel0
15:14
x
0 I/O P0.7 GPIO 0 General purpose digital input/output pin.
2 I/O SCK1 SSP 1 Serial Clock for SSP1.
3 O MAT2.1 Timer 2 Match output for Timer 2, channel 1.
64 P0.6/SSEL1/MAT2.0 pinsel0
13:12
x
0 I/O P0.6 GPIO 0 General purpose digital input/output pin.
2 I/O SSEL1 SSP 1 Slave Select for SSP1.
3 O MAT2.0 Timer 2 Match output for Timer 2, channel 0.
65 P4.28/MAT2.0/TXD3 pinsel9
25:24
x
0 I/O P4.28 GPIO 4 General purpose digital input/output pin.
2 O MAT2.0 Timer 2 Match output for Timer 2, channel 0.
3 O TXD3 UART 3 Transmitter output for UART3.
66 VSS I VSS Main ground: 0 V reference.
67 VDD(REG)(3V3) I VDD(REG)(3V3) Main 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip voltage regulator only.
68 P4.29/MAT2.1/RXD3 pinsel9
27:26
x
0 I/O P4.29 GPIO 4 General purpose digital input/output pin.
2 O MAT2.1 Timer 2 Match output for Timer 2, channel 1.
3 I RXD3 UART 3 Receiver input for UART3.
69 P1.15 I/O P1.15 GPIO 1 General purpose digital input/output pin.
70 P1.14 I/O P1.14 GPIO 1 General purpose digital input/output pin.
71 P1.10 I/O P1.10 GPIO 1 General purpose digital input/output pin.
72 P1.9 I/O P1.9 GPIO 1 General purpose digital input/output pin.
73 P1.8 I/O P1.8 GPIO 1 General purpose digital input/output pin.
74 P1.4 I/O P1.4 GPIO 1 General purpose digital input/output pin.
75 P1.1 I/O P1.1 GPIO 1 General purpose digital input/output pin.
76 P1.0 I/O P1.0 GPIO 1 General purpose digital input/output pin.
77 VDD(3V3) I VDD(3V3) Main 3.3 V supply voltage: This is the power supply voltage for I/O other than pins in the Vbat domain.
78 VSS I VSS Main ground: 0 V reference.
79 P0.2/TXD0/AD0.7 pinsel0
5:4
x
0 I/O P0.2 GPIO 0 General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled.
1 O TXD0 UART 0 Transmitter output for UART0.
2 I AD0.7 ADC A/D converter 0, input 7.
80 P0.3/RXD0/AD0.6 pinsel0
7:6
x
0 I/O P0.3 GPIO 0 General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled.
1 I RXD0 UART 0 Receiver input for UART0.
2 I AD0.6 ADC A/D converter 0, input 6.


Function Blocks.

Function block ADC

Analog-to-Digital Converter
Signal Pin I/O Description
AD0.2 7 I A/D converter 0, input 2.
AD0.3 6 I A/D converter 0, input 3.
AD0.4 18 I A/D converter 0, input 4.
AD0.5 17 I A/D converter 0, input 5.
AD0.6 80 I A/D converter 0, input 6.
AD0.7 79 I A/D converter 0, input 7.
VREFP 10 I ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. The voltage level on this pin is used as a reference for ADC and DAC.
Note: this pin should be tied to 3.3v if the ADC and DAC are not used.
VREFN 12 I ADC negative reference voltage: This should be the same voltage as VSS but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC.
VDDA 8 P analog 3.3 V pad supply voltage: This can be connected to the same supply as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. Note: this pin should be tied to 3.3v if the ADC and DAC are not used.
VSSA 9 P analog ground: 0 V reference. This should be the same voltage as VSS, but should be isolated to minimize noise and error.


Function block CAN

CAN
Signal Pins I/O Description
RD1 37 I CAN1 receiver input.
TD1 38 44 O CAN1 transmitter output.


Function block GPIO

General Purpose I/O Pins
Generic Block Signals
Signal I/O Description
Pn.0 I/O General purpose input/output. These are typically shared with other peripherals functions and will therefore not all be available in an application. Packaging options may affect the number of GPIOs available in a particular device. Some pins may be limited by requirements of the alternate functions of the pin. For example, the pins containing the I2C0 functions are open-drain for any function selected on that pin. Details may be found in Section 7–1.1 of the user manual.
Signals for GPIO0
Signal Pin I/O Description
P0.0 37 I/O General purpose digital input/output pin.
P0.1 38 I/O General purpose digital input/output pin.
P0.2 79 I/O General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled.
P0.3 80 I/O General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled.
P0.6 64 I/O General purpose digital input/output pin.
P0.7 63 I/O General purpose digital input/output pin.
P0.8 62 I/O General purpose digital input/output pin.
P0.9 61 I/O General purpose digital input/output pin.
P0.10 39 I/O General purpose digital input/output pin.
P0.11 40 I/O General purpose digital input/output pin.
P0.15 47 I/O General purpose digital input/output pin.
P0.16 48 I/O General purpose digital input/output pin.
P0.17 46 I/O General purpose digital input/output pin.
P0.18 45 I/O General purpose digital input/output pin.
P0.22 44 I/O General purpose digital input/output pin.
P0.25 7 I/O General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled.
P0.26 6 I/O General purpose digital input/output pin. When configured as an ADC input or DAC output, the digital section of the pad is disabled.
P0.29 22 I/O General purpose digital input/output pin. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only).
P0.30 23 I/O General purpose digital input/output pin. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only).
Signals for GPIO1
Signal Pin I/O Description
P1.0 76 I/O General purpose digital input/output pin.
P1.1 75 I/O General purpose digital input/output pin.
P1.4 74 I/O General purpose digital input/output pin.
P1.8 73 I/O General purpose digital input/output pin.
P1.9 72 I/O General purpose digital input/output pin.
P1.10 71 I/O General purpose digital input/output pin.
P1.14 70 I/O General purpose digital input/output pin.
P1.15 69 I/O General purpose digital input/output pin.
P1.18 25 I/O General purpose digital input/output pin.
P1.19 26 I/O General purpose digital input/output pin.
P1.20 27 I/O General purpose digital input/output pin.
P1.22 28 I/O General purpose digital input/output pin.
P1.23 29 I/O General purpose digital input/output pin.
P1.24 30 I/O General purpose digital input/output pin.
P1.25 31 I/O General purpose digital input/output pin.
P1.26 32 I/O General purpose digital input/output pin.
P1.28 35 I/O General purpose digital input/output pin.
P1.29 36 I/O General purpose digital input/output pin.
P1.30 18 I/O General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled.
P1.31 17 I/O General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled.
Signals for GPIO2
Signal Pin I/O Description
P2.0 60 I/O General purpose digital input/output pin.
P2.1 59 I/O General purpose digital input/output pin.
P2.2 58 I/O General purpose digital input/output pin.
P2.3 55 I/O General purpose digital input/output pin.
P2.4 54 I/O General purpose digital input/output pin.
P2.5 53 I/O General purpose digital input/output pin.
P2.6 52 I/O General purpose digital input/output pin.
P2.7 51 I/O General purpose digital input/output pin.
P2.8 50 I/O General purpose digital input/output pin.
P2.9 49 I/O General purpose digital input/output pin.
P2.10 41 I/O General purpose digital input/output pin. 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. Note: A LOW on this pin while !RESET is LOW forces the on-chip bootloader to take over control of the part after a reset and go into ISP mode. See Section 32–1.
Signals for GPIO4
Signal Pin I/O Description
P4.28 65 I/O General purpose digital input/output pin.
P4.29 68 I/O General purpose digital input/output pin.


Function block I2C

I2C interface
Generic Block Signals
Signal I/O Description
SDAn I/O I2C Serial Data
SCLn I/O I2C Serial Clock
Signals for I2C1
Signal Pin I/O Description
SDA1 37 I/O I2C1 data input/output (this pin is not fully compliant with the I2C-bus specification, see Section 19–4 for details).
SCL1 38 I/O I2C1 clock input/output (this pin is not fully compliant with the I2C-bus specification, see Section 19–4 for details).
Signals for I2C2
Signal Pin I/O Description
SDA2 39 I/O I2C2 data input/output (this is not an open-drain pin).
SCL2 40 I/O I2C2 clock input/output (this is not an open-drain pin).


Function block JTAG

JTAG
Signal Pin I/O Description
TCK 5 I Test Clock for JTAG interface.
TMS 3 I Test Mode Select for JTAG interface.
TDI 2 I Test Data in for JTAG interface.
TDO 1 O Test Data out for JTAG interface.
!TRST 4 I Test Reset for JTAG interface.


Function block Main

Main
Signal Pins I/O Description
!RESET 14 I External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. This is a 5 V tolerant pad with a 20 ns glitch filter, TTL levels and hysteresis.
!RSTOUT 11 O This is a 3.3 V pin. A LOW on this pin indicates that the LPC17xx is in a Reset state.
XTAL1 19 I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 20 O Output from the oscillator amplifier.
VSS 24 33 43 57 66 78 I ground: 0 V reference.
VDD(3V3) 21 42 56 77 I 3.3 V supply voltage: This is the power supply voltage for I/O other than pins in the Vbat domain.
VDD(REG)(3V3) 34 67 I 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip voltage regulator only.
!EINT0 41 I External interrupt 0 input.
NMI 41 I Non-maskable interrupt input.


Function block Motor-PWM

Motor Control PWM
Signal Pin I/O Description
MCOA0 26 O Motor control PWM channel 0, output A.
MCOA1 31 O Motor control PWM channel 1, output A.
MCOA2 35 O Motor control PWM channel 2, output A.
MCOB0 28 O Motor control PWM channel 0, output B.
MCOB1 32 O Motor control PWM channel 1, output B.
MCOB2 36 O Motor control PWM channel 2, output B.
MCI0 27 I Motor control PWM channel 0 input. Also Quadrature Encoder Interface PHA input.
MCI1 29 I Motor control PWM channel 1 input. Also Quadrature Encoder Interface PHB input.
MCI2 30 I Motor control PWM channel 2 input. Also Quadrature Encoder Interface INDEX input.


Function block PWM

Pulse Width Modulator
Signal Pins I/O Description
PWM1.1 25 60 O Pulse Width Modulator 1, channel 1 output.
PWM1.2 27 59 O Pulse Width Modulator 1, channel 2 output.
PWM1.3 58 O Pulse Width Modulator 1, channel 3 output.
PWM1.4 29 55 O Pulse Width Modulator 1, channel 4 output.
PWM1.5 30 54 O Pulse Width Modulator 1, channel 5 output.
PWM1.6 32 53 O Pulse Width Modulator 1, channel 6 output.
PCAP1.0 35 52 I Capture input for PWM1, channel 0.
PCAP1.1 36 I Capture input for PWM1, channel 1.


Function block RTC

Real-Time Clock and backup registers
Signal Pin I/O Description
RTCX1 13 I Input to the RTC oscillator circuit.
RTCX2 15 O Output from the RTC oscillator circuit.
VBAT 16 I RTC domain power supply: 3.3 V on this pin supplies the power to the RTC peripheral.


Function block SPI

SPI
Signal Pin I/O Description
SCK 47 I/O Serial clock for SPI.
SSEL 48 I Slave Select for SPI.
MISO 46 I/O Master In Slave Out for SPI.
MOSI 45 I/O Master Out Slave In for SPI.


Function block SSP

SSP0/1 interface
Generic Block Signals
Signal I/O Description
SCKn I/O SCK CLK SK Serial Clock. SCK/CLK/SK is a clock signal used to synchronize the transfer of data. It is driven by the master and received by the slave. When the SPI interface is used, the clock is programmable to be active-high or active-low, otherwise it is always active-high. SCK1 only switches during a data transfer. Any other time, the SSPn interface either holds it in its inactive state, or does not drive it (leaves it in high-impedance state).
SSELn I/O SSEL FS CS Frame Sync/Slave Select. When the SSPn interface is a bus master, it drives this signal to an active state before the start of serial data, and then releases it to an inactive state after the serial data has been sent. The active state of this signal can be high or low depending upon the selected bus and mode. When the SSPn is a bus slave, this signal qualifies the presence of data from the Master, according to the protocol in use. When there is just one bus master and one bus slave, the Frame Sync or Slave Select signal from the Master can be connected directly to the slave's corresponding input. When there is more than one slave on the bus, further qualification of their Frame Select/Slave Select inputs will typically be necessary to prevent more than one slave from responding to a transfer.
MISOn I/O SPI signal MISO, SSI signal DR(M) / DX(S), Microwire signal SI(M) / SO(S) : Master In Slave Out. The MISO signal transfers serial data from the slave to the master. When the SSPn is a slave, serial data is output on this signal. When the SSPn is a master, it clocks in serial data from this signal. When the SSPn is a slave and is not selected by FS/SSEL, it does not drive this signal (leaves it in high-impedance state).
MOSIn I/O SPI signal MOSI, SSI signal DX(M) / DR(S), Microwire signal SO(M) / SI(S) : Master Out Slave In. The MOSI signal transfers serial data from the master to the slave. When the SSPn is a master, it outputs serial data on this signal. When the SSPn is a slave, it clocks in serial data from this signal.
Signals for SSP0
Signal Pins I/O Description
SCK0 27 47 I/O Serial clock for SSP0.
SSEL0 48 I/O Slave Select for SSP0.
MISO0 29 46 I/O Master In Slave Out for SSP0.
MOSI0 30 45 I/O Master Out Slave In for SSP0.
Signals for SSP1
Signal Pins I/O Description
SCK1 17 63 I/O Serial Clock for SSP1.
SSEL1 64 I/O Slave Select for SSP1.
MISO1 62 I/O Master In Slave Out for SSP1.
MOSI1 61 I/O Master Out Slave In for SSP1.


Function block SWDEBUG

Serial Wire Debug
Signal Pin I/O Description
SWDCLK 5 I Serial wire clock.
SWDIO 3 I Serial wire debug data input/output.
SWO 1 O Serial wire trace output.


Function block Timer

Timer 0/1/2/3
Generic Block Signals
Signal I/O Description
CAPn.0 I Capture Signals- A transition on a capture pin can be configured to load one of the Capture Registers with the value in the Timer Counter and optionally generate an interrupt. Capture functionality can be selected from a number of pins. When more than one pin is selected for a Capture input on a single TIMER0/1 channel, the pin with the lowest Port number is used Timer/Counter block can select a capture signal as a clock source instead of the PCLK derived clock.
For more details see Section 21–6.3 of the user manual.
MATn.0 O External Match Output - When a match register (MR3:0) equals the timer counter (TC) this output can either toggle, go low, go high, or do nothing. The External Match Register (EMR) controls the functionality of this output. Match Output functionality can be selected on a number of pins in parallel.
Signals for Timer0
Signal Pin I/O Description
CAP0.0 32 I Capture input for Timer 0, channel 0.
MAT0.0 35 O Match output for Timer 0, channel 0.
MAT0.1 36 O Match output for Timer 0, channel 1.
Signals for Timer1
Signal Pin I/O Description
CAP1.0 25 I Capture input for Timer 1, channel 0.
CAP1.1 26 I Capture input for Timer 1, channel 1.
MAT1.0 28 O Match output for Timer 1, channel 0.
MAT1.1 31 O Match output for Timer 1, channel 1.
Signals for Timer2
Signal Pins I/O Description
MAT2.0 64 65 O Match output for Timer 2, channel 0.
MAT2.1 63 68 O Match output for Timer 2, channel 1.
MAT2.2 62 O Match output for Timer 2, channel 2.
MAT2.3 61 O Match output for Timer 2, channel 3.
Signals for Timer3
Signal Pin I/O Description
MAT3.0 39 O Match output for Timer 3, channel 0.
MAT3.1 40 O Match output for Timer 3, channel 1.


Function block Trace

Trace
Signal Pin I/O Description
TRACECLK 52 I Trace Clock.
TRACEDATA0 53 O Trace data, bit 0.
TRACEDATA1 54 O Trace data, bit 1.
TRACEDATA2 55 O Trace data, bit 2.
TRACEDATA3 58 O Trace data, bit 3.


Function block UART

UART0/1/2/3
Generic Block Signals
Signal I/O Description
RXDn I Serial Input. Serial receive data.
TXDn O Serial Output. Serial transmit data.
CTSn I Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted data via TXDn from the UARTn. In normal operation of the modem interface (U1MCR.4 = 0), the complement value of this signal is stored in U1MSR.4. State change information is stored in U1MSR.0 and is a source for a priority level 4 interrupt, if enabled (U1IER.3 = 1). Clear to send. CTSn is an asynchronous, active low modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the Modem Status Register (MSR) indicates that CTSn has changed states since the last read from the MSR. If the modem status interrupt is enabled when CTSn changes levels and the auto-cts mode is not enabled, an interrupt is generated. CTSn is also used in the auto-cts mode to control the transmitter.
DCDn I Data Carrier Detect. Active low signal indicates if the external modem has established a communication link with the UARTn and data may be exchanged. In normal operation of the modem interface (U1MCR.4=0), the complement value of this signal is stored in U1MSR.7. State change information is stored in U1MSR3 and is a source for a priority level 4 interrupt, if enabled (U1IER.3 = 1).
DSRn I Data Set Ready. Active low signal indicates if the external modem is ready to establish a communications link with the UARTn. In normal operation of the modem interface (U1MCR.4 = 0), the complement value of this signal is stored in U1MSR.5. State change information is stored in U1MSR.1 and is a source for a priority level 4 interrupt, if enabled (U1IER.3 = 1).
DTRn O Data Terminal Ready. Active low signal indicates that the UARTn is ready to establish connection with external modem. The complement value of this signal is stored in U1MCR.0.
The DTR pin can also be used as an RS-485/EIA-485 output enable signal.
RIn I Ring Indicator. Active low signal indicates that a telephone ringing signal has been detected by the modem. In normal operation of the modem interface (U1MCR.4 = 0), the complement value of this signal is stored in U1MSR.6. State change information is stored in U1MSR.2 and is a source for a priority level 4 interrupt, if enabled (U1IER.3 = 1).
RTSn O Request To Send. Active low signal indicates that the UARTn would like to transmit data to the external modem. The complement value of this signal is stored in U1MCR.1. In auto-rts mode, RTSn is used to control the transmitter FIFO threshold logic. Request to send. RTSn is an active low signal informing the modem or data set that the UART is ready to receive data. RTSn is set to the active (low) level by setting the RTS modem control register bit and is set to the inactive (high) level either as a result of a system reset or during loop-back mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-rts mode, RTSn is controlled by the transmitter FIFO threshold logic. The RTS pin can also be used as an RS-485/EIA-485 output enable signal.
Signals for UART0
Signal Pin I/O Description
RXD0 80 I Receiver input for UART0.
TXD0 79 O Transmitter output for UART0.
Signals for UART1
Signal Pins I/O Description
RXD1 48 59 I Receiver input for UART1.
TXD1 47 60 O Transmitter output for UART1.
CTS1 46 58 I Clear to Send input for UART1.
DCD1 45 55 I Data Carrier Detect input for UART1.
DSR1 54 I Data Set Ready input for UART1.
DTR1 53 O Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal.
RI1 52 I Ring Indicator input for UART1.
RTS1 44 51 O Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal.
Signals for UART2
Signal Pins I/O Description
RXD2 40 49 I Receiver input for UART2.
TXD2 39 50 O Transmitter output for UART2.
Signals for UART3
Signal Pins I/O Description
RXD3 6 38 68 I Receiver input for UART3.
TXD3 7 37 65 O Transmitter output for UART3.


Function block USB-Device

USB device controller
Signal Pin I/O Description
VBUS 18 I Monitors the presence of USB bus power. Note: This signal must be HIGH for USB reset to occur.
USB_CONNECT 49 O Signal used to switch an external 1.5 kΩ resistor under software control. Used with the SoftConnect USB feature.
USB_UP_LED 25 O USB GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend.
USB_D+ 22 I/O USB bidirectional D+ line.
USB_D- 23 I/O USB bidirectional D- line.



pinsel registers.

pinsel0 pinsel1 pinsel2 pinsel3 pinsel4
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
pinsel5 pinsel6 pinsel7 pinsel8 pinsel9
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000


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