LPC2364 Pin function table.

Pin Symbol Pinsel
reg
Pin
sel
ix
I/O Pin
Function
Function
Block
Description
1 TDO O TDO JTAG Test Data out for JTAG interface.
2 TDI I TDI JTAG Test Data in for JTAG interface.
3 TMS I TMS JTAG Test Mode Select for JTAG interface.
4 !TRST I !TRST JTAG Test Reset for JTAG interface.
5 TCK I TCK JTAG Test Clock for JTAG interface. This clock must be slower than 1/6 of the CPU clock (CCLK) for the JTAG interface to operate
6 P0.26/AD0.3/AOUT/RXD3 pinsel1
21:20
x
0 I/O P0.26 GPIO 0 General purpose digital input/output pin.
1 I AD0.3 ADC A/D converter 0, input 3.
2 O AOUT DAC D/A converter output.
3 I RXD3 UART 3 Receiver input for UART3.
7 P0.25/AD0.2/I2SRX_SDA/TXD3 pinsel1
19:18
x
0 I/O P0.25 GPIO 0 General purpose digital input/output pin.
1 I AD0.2 ADC A/D converter 0, input 2.
2 I/O I2SRX_SDA I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification.
3 O TXD3 UART 3 Transmitter output for UART3.
8 P0.24/AD0.1/I2SRX_WS/CAP3.1 pinsel1
17:16
x
0 I/O P0.24 GPIO 0 General purpose digital input/output pin.
1 I AD0.1 ADC A/D converter 0, input 1.
2 I/O I2SRX_WS I2S Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification.
3 I CAP3.1 Timer/Counter 3 Capture input for Timer 3, channel 1.
9 P0.23/AD0.0/I2SRX_CLK/CAP3.0 pinsel1
15:14
x
0 I/O P0.23 GPIO 0 General purpose digital input/output pin.
1 I AD0.0 ADC A/D converter 0, input 0.
2 I/O I2SRX_CLK I2S Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.
3 I CAP3.0 Timer/Counter 3 Capture input for Timer 3, channel 0.
10 VDDA I VDDA ADC analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC.
11 VSSA I VSSA ADC analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error.
12 VREF I VREF ADC ADC reference: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. Level on this pin is used as reference for ADC and DAC.
13 VDD(DCDC)(3V3) I VDD(DCDC)(3V3) Main 3.3 V DC-to-DC converter supply voltage: This is the supply voltage for the on-chip DC-to-DC converter only.
14 !RSTOUT O !RSTOUT Main This is a 3.3 V pin. LOW on this pin indicates LPC23xx being in Reset state.
15 VSS I VSS Main ground: 0 V reference.
16 RTCX1 I RTCX1 Battery Input to the RTC oscillator circuit.
17 !RESET I !RESET Main External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
18 RTCX2 O RTCX2 Battery Output from the RTC oscillator circuit.
19 VBAT I VBAT Battery RTC pin power supply: 3.3 V on this pin supplies the power to the RTC peripheral.
20 P1.31/SCK1/AD0.5 pinsel3
31:30
x
0 I/O P1.31 GPIO 1 General purpose digital input/output pin.
2 I/O SCK1 SSP 1 Serial clock for SSP1.
3 I AD0.5 ADC A/D converter 0, input 5.
21 P1.30/VBUS/AD0.4 pinsel3
29:28
x
0 I/O P1.30 GPIO 1 General purpose digital input/output pin.
2 I VBUS USB Monitors the presence of USB bus power.Note: This signal must be HIGH for USB reset to occur.
3 I AD0.4 ADC A/D converter 0, input 4.
22 XTAL1 I XTAL1 Main Input to the oscillator circuit and internal clock generator circuits.
23 XTAL2 O XTAL2 Main Output from the oscillator amplifier.
24 P0.28/SCL0 pinsel1
25:24
x
0 I/O P0.28 GPIO 0 General purpose digital input/output pin. Output is open-drain.
1 I/O SCL0 I2C 0 I2C0 clock input/output. Open-drain output (for I2C-bus compliance).
25 P0.27/SDA0 pinsel1
23:22
x
0 I/O P0.27 GPIO 0 General purpose digital input/output pin. Output is open-drain.
1 I/O SDA0 I2C 0 I2C0 data input/output. Open-drain output (for I2C-bus compliance).
26 P3.26/MAT0.1/PWM1.3 pinsel7
21:20
x
0 I/O P3.26 GPIO 3 General purpose digital input/output pin.
2 O MAT0.1 Timer/Counter 0 Match output for Timer 0, channel 1.
3 O PWM1.3 PWM Pulse Width Modulator 1, channel 3 output.
27 P3.25/MAT0.0/PWM1.2 pinsel7
19:18
x
0 I/O P3.25 GPIO 3 General purpose digital input/output pin.
2 O MAT0.0 Timer/Counter 0 Match output for Timer 0, channel 0.
3 O PWM1.2 PWM Pulse Width Modulator 1, channel 2 output.
28 VDD(3V3) I VDD(3V3) Main 3.3 V supply voltage: This is the power supply voltage for the I/O ports.
29 P0.29/USB_D+ pinsel1
27:26
x
0 I/O P0.29 GPIO 0 General purpose digital input/output pin.
1 I/O USB_D+ USB USB bidirectional D+ line.
30 P0.30/USB_D- pinsel1
29:28
x
0 I/O P0.30 GPIO 0 General purpose digital input/output pin.
1 I/O USB_D- USB USB bidirectional D- line.
31 VSS I VSS Main ground: 0 V reference.
32 P1.18/USB_UP_LED/PWM1.1/CAP1.0 pinsel3
5:4
x
0 I/O P1.18 GPIO 1 General purpose digital input/output pin.
1 O USB_UP_LED USB USB GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend.
2 O PWM1.1 PWM Pulse Width Modulator 1, channel 1 output.
3 I CAP1.0 Timer/Counter 1 Capture input for Timer 1, channel 0.
33 P1.19/CAP1.1 pinsel3
7:6
x
0 I/O P1.19 GPIO 1 General purpose digital input/output pin.
1 I CAP1.1 Timer/Counter 1 Capture input for Timer 1, channel 1.
34 P1.20/PWM1.2/SCK0 pinsel3
9:8
x
0 I/O P1.20 GPIO 1 General purpose digital input/output pin.
1 O PWM1.2 PWM Pulse Width Modulator 1, channel 2 output.
2 I/O SCK0 SSP 0 Serial clock for SSP0.
35 P1.21/PWM1.3/SSEL0 pinsel3
11:10
x
0 I/O P1.21 GPIO 1 General purpose digital input/output pin.
1 O PWM1.3 PWM Pulse Width Modulator 1, channel 3 output.
2 I/O SSEL0 SSP 0 Slave Select for SSP0.
36 P1.22/MAT1.0 pinsel3
13:12
x
0 I/O P1.22 GPIO 1 General purpose digital input/output pin.
1 O MAT1.0 Timer/Counter 1 Match output for Timer 1, channel 0.
37 P1.23/PWM1.4/MISO0 pinsel3
15:14
x
0 I/O P1.23 GPIO 1 General purpose digital input/output pin.
1 O PWM1.4 PWM Pulse Width Modulator 1, channel 4 output.
2 I/O MISO0 SSP 0 Master In Slave Out for SSP0.
38 P1.24/PWM1.5/MOSI0 pinsel3
17:16
x
0 I/O P1.24 GPIO 1 General purpose digital input/output pin.
1 O PWM1.5 PWM Pulse Width Modulator 1, channel 5 output.
2 I/O MOSI0 SSP 0 Master Out Slave In for SSP0.
39 P1.25/MAT1.1 pinsel3
19:18
x
0 I/O P1.25 GPIO 1 General purpose digital input/output pin.
1 O MAT1.1 Timer/Counter 1 Match output for Timer 1, channel 1.
40 P1.26/PWM1.6/CAP0.0 pinsel3
21:20
x
0 I/O P1.26 GPIO 1 General purpose digital input/output pin.
1 O PWM1.6 PWM Pulse Width Modulator 1, channel 6 output.
2 I CAP0.0 Timer/Counter 0 Capture input for Timer 0, channel 0.
41 VSS I VSS Main ground: 0 V reference.
42 VDD(DCDC)(3V3) I VDD(DCDC)(3V3) Main 3.3 V DC-to-DC converter supply voltage: This is the supply voltage for the on-chip DC-to-DC converter only.
43 P1.27/CAP0.1 pinsel3
23:22
x
0 I/O P1.27 GPIO 1 General purpose digital input/output pin.
1 I CAP0.1 Timer/Counter 0 Capture input for Timer 0, channel 1.
44 P1.28/PCAP1.0/MAT0.0 pinsel3
25:24
x
0 I/O P1.28 GPIO 1 General purpose digital input/output pin.
1 I PCAP1.0 PWM Capture input for PWM1, channel 0.
2 O MAT0.0 Timer/Counter 0 Match output for Timer 0, channel 0.
45 P1.29/PCAP1.1/MAT0.1 pinsel3
27:26
x
0 I/O P1.29 GPIO 1 General purpose digital input/output pin.
1 I PCAP1.1 PWM Capture input for PWM1, channel 1.
2 O MAT0.1 Timer/Counter 0 Match output for Timer 0, channel 1.
46 P0.0/RD1/TXD3/SDA1 pinsel0
1:0
x
0 I/O P0.0 GPIO 0 General purpose digital input/output pin.
1 I RD1 CAN 1 CAN1 receiver input.
2 O TXD3 UART 3 Transmitter output for UART3.
3 I/O SDA1 I2C 1 I2C1 data input/output. (this is not an open-drain pin).
47 P0.1/TD1/RXD3/SCL1 pinsel0
3:2
x
0 I/O P0.1 GPIO 0 General purpose digital input/output pin.
1 O TD1 CAN 1 CAN1 transmitter output.
2 I RXD3 UART 3 Receiver input for UART3.
3 I/O SCL1 I2C 1 I2C1 clock input/output. (this is not an open-drain pin).
48 P0.10/TXD2/SDA2/MAT3.0 pinsel0
21:20
x
0 I/O P0.10 GPIO 0 General purpose digital input/output pin.
1 O TXD2 UART 2 Transmitter output for UART2.
2 I/O SDA2 I2C 2 I2C2 data input/output. (this is not an open-drain pin).
3 O MAT3.0 Timer/Counter 3 Match output for Timer 3, channel 0.
49 P0.11/RXD2/SCL2/MAT3.1 pinsel0
23:22
x
0 I/O P0.11 GPIO 0 General purpose digital input/output pin.
1 I RXD2 UART 2 Receiver input for UART2.
2 I/O SCL2 I2C 2 I2C2 clock input/output. (this is not an open-drain pin).
3 O MAT3.1 Timer/Counter 3 Match output for Timer 3, channel 1.
50 P2.13/!EINT3/I2STX_SDA pinsel4
27:26
x
0 I/O P2.13 GPIO 2 General purpose digital input/output pin.
1 I !EINT3 ExtInt 3 External interrupt 3 input.
3 I/O I2STX_SDA I2S Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification.
51 P2.12/!EINT2/I2STX_WS pinsel4
25:24
x
0 I/O P2.12 GPIO 2 General purpose digital input/output pin.
1 I !EINT2 ExtInt 2 External interrupt 2 input.
3 I/O I2STX_WS I2S Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification.
52 P2.11/!EINT1/I2STX_CLK pinsel4
23:22
x
0 I/O P2.11 GPIO 2 General purpose digital input/output pin.
1 I !EINT1 ExtInt 1 External interrupt 1 input.
3 I/O I2STX_CLK I2S Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.
53 P2.10/!EINT0 pinsel4
21:20
x
0 I/O P2.10 GPIO 2 General purpose digital input/output pin. Note: LOW on this pin after reset forces on-chip bootloader to take over control.
1 I !EINT0 ExtInt 0 External interrupt 0 input.
54 VDD(3V3) I VDD(3V3) Main 3.3 V supply voltage: This is the power supply voltage for the I/O ports.
55 VSS I VSS Main ground: 0 V reference.
56 P0.22/RTS1/TD1 pinsel1
13:12
x
0 I/O P0.22 GPIO 0 General purpose digital input/output pin.
1 O RTS1 UART 1 Request to Send output for UART1.
3 O TD1 CAN 1 CAN1 transmitter output.
57 P0.21/RI1/RD1 pinsel1
11:10
x
0 I/O P0.21 GPIO 0 General purpose digital input/output pin.
1 I RI1 UART 1 Ring Indicator input for UART1.
3 I RD1 CAN 1 CAN1 receiver input.
58 P0.20/DTR1/SCL1 pinsel1
9:8
x
0 I/O P0.20 GPIO 0 General purpose digital input/output pin.
1 O DTR1 UART 1 Data Terminal Ready output for UART1.
3 I/O SCL1 I2C 1 I2C1 clock input/output. (this is not an open-drain pin).
59 P0.19/DSR1/SDA1 pinsel1
7:6
x
0 I/O P0.19 GPIO 0 General purpose digital input/output pin.
1 I DSR1 UART 1 Data Set Ready input for UART1.
3 I/O SDA1 I2C 1 I2C1 data input/output. (this is not an open-drain pin).
60 P0.18/DCD1/MOSI0/MOSI pinsel1
5:4
x
0 I/O P0.18 GPIO 0 General purpose digital input/output pin.
1 I DCD1 UART 1 Data Carrier Detect input for UART1.
2 I/O MOSI0 SSP 0 Master Out Slave In for SSP0.
3 I/O MOSI SPI Master Out Slave In for SPI.
61 P0.17/CTS1/MISO0/MISO pinsel1
3:2
x
0 I/O P0.17 GPIO 0 General purpose digital input/output pin.
1 I CTS1 UART 1 Clear to Send input for UART1.
2 I/O MISO0 SSP 0 Master In Slave Out for SSP0.
3 I/O MISO SPI Master In Slave Out for SPI.
62 P0.15/TXD1/SCK0/SCK pinsel0
31:30
x
0 I/O P0.15 GPIO 0 General purpose digital input/output pin.
1 O TXD1 UART 1 Transmitter output for UART1.
2 I/O SCK0 SSP 0 Serial clock for SSP0.
3 I/O SCK SPI Serial clock for SPI.
63 P0.16/RXD1/SSEL0/SSEL pinsel1
1:0
x
0 I/O P0.16 GPIO 0 General purpose digital input/output pin.
1 I RXD1 UART 1 Receiver input for UART1.
2 I/O SSEL0 SSP 0 Slave Select for SSP0.
3 I/O SSEL SPI Slave Select for SPI.
64 P2.9/USB_CONNECT/RXD2/EXTIN0 pinsel4
19:18
x
0 I/O P2.9 GPIO 2 General purpose digital input/output pin.
1 O USB_CONNECT USB Signal used to switch an external 1.5 kOhm resistor under software control. Used with the SoftConnect USB feature.
2 I RXD2 UART 2 Receiver input for UART2.
3 I EXTIN0 EmbeddedTrace External Trigger Input.
65 P2.8/TD2/TXD2/TRACEPKT3 pinsel4
17:16
x
0 I/O P2.8 GPIO 2 General purpose digital input/output pin.
1 O TD2 CAN 2 CAN2 transmitter output.
2 O TXD2 UART 2 Transmitter output for UART2.
3 O TRACEPKT3 EmbeddedTrace Trace Packet, bit 0.
66 P2.7/RD2/RTS1/TRACEPKT2 pinsel4
15:14
x
0 I/O P2.7 GPIO 2 General purpose digital input/output pin.
1 I RD2 CAN 2 CAN2 receiver input.
2 O RTS1 UART 1 Request to Send output for UART1.
3 O TRACEPKT2 EmbeddedTrace Trace Packet, bit 0.
67 P2.6/PCAP1.0/RI1/TRACEPKT1 pinsel4
13:12
x
0 I/O P2.6 GPIO 2 General purpose digital input/output pin.
1 I PCAP1.0 PWM Capture input for PWM1, channel 0.
2 I RI1 UART 1 Ring Indicator input for UART1.
3 O TRACEPKT1 EmbeddedTrace Trace Packet, bit 0.
68 P2.5/PWM1.6/DTR1/TRACEPKT0 pinsel4
11:10
x
0 I/O P2.5 GPIO 2 General purpose digital input/output pin.
1 O PWM1.6 PWM Pulse Width Modulator 1, channel 6 output.
2 O DTR1 UART 1 Data Terminal Ready output for UART1.
3 O TRACEPKT0 EmbeddedTrace Trace Packet, bit 0.
69 P2.4/PWM1.5/DSR1/TRACESYNC pinsel4
9:8
x
0 I/O P2.4 GPIO 2 General purpose digital input/output pin.
1 O PWM1.5 PWM Pulse Width Modulator 1, channel 5 output.
2 I DSR1 UART 1 Data Set Ready input for UART1.
3 O TRACESYNC EmbeddedTrace Trace Synchronization.
70 P2.3/PWM1.4/DCD1/PIPESTAT2 pinsel4
7:6
x
0 I/O P2.3 GPIO 2 General purpose digital input/output pin.
1 O PWM1.4 PWM Pulse Width Modulator 1, channel 4 output.
2 I DCD1 UART 1 Data Carrier Detect input for UART1.
3 O PIPESTAT2 EmbeddedTrace Pipeline Status, bit 0.
71 VDD(3V3) I VDD(3V3) Main 3.3 V supply voltage: This is the power supply voltage for the I/O ports.
72 VSS I VSS Main ground: 0 V reference.
73 P2.2/PWM1.3/CTS1/PIPESTAT1 pinsel4
5:4
x
0 I/O P2.2 GPIO 2 General purpose digital input/output pin.
1 O PWM1.3 PWM Pulse Width Modulator 1, channel 3 output.
2 I CTS1 UART 1 Clear to Send input for UART1.
3 O PIPESTAT1 EmbeddedTrace Pipeline Status, bit 0.
74 P2.1/PWM1.2/RXD1/PIPESTAT0 pinsel4
3:2
x
0 I/O P2.1 GPIO 2 General purpose digital input/output pin.
1 O PWM1.2 PWM Pulse Width Modulator 1, channel 2 output.
2 I RXD1 UART 1 Receiver input for UART1.
3 O PIPESTAT0 EmbeddedTrace Pipeline Status, bit 0.
75 P2.0/PWM1.1/TXD1/TRACECLK pinsel4
1:0
x
0 I/O P2.0 GPIO 2 General purpose digital input/output pin.
1 O PWM1.1 PWM Pulse Width Modulator 1, channel 1 output.
2 O TXD1 UART 1 Transmitter output for UART1.
3 O TRACECLK EmbeddedTrace TRACECLK -- Trace Clock.
76 P0.9/I2STX_SDA/MOSI1/MAT2.3 pinsel0
19:18
x
0 I/O P0.9 GPIO 0 General purpose digital input/output pin.
1 I/O I2STX_SDA I2S Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification.
2 I/O MOSI1 SSP 1 Master Out Slave In for SSP1.
3 O MAT2.3 Timer/Counter 2 Match output for Timer 2, channel 3.
77 P0.8/I2STX_WS/MISO1/MAT2.2 pinsel0
17:16
x
0 I/O P0.8 GPIO 0 General purpose digital input/output pin.
1 I/O I2STX_WS I2S Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification.
2 I/O MISO1 SSP 1 Master In Slave Out for SSP1.
3 O MAT2.2 Timer/Counter 2 Match output for Timer 2, channel 2.
78 P0.7/I2STX_CLK/SCK1/MAT2.1 pinsel0
15:14
x
0 I/O P0.7 GPIO 0 General purpose digital input/output pin.
1 I/O I2STX_CLK I2S Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.
2 I/O SCK1 SSP 1 Serial clock for SSP1.
3 O MAT2.1 Timer/Counter 2 Match output for Timer 2, channel 1.
79 P0.6/I2SRX_SDA/SSEL1/MAT2.0 pinsel0
13:12
x
0 I/O P0.6 GPIO 0 General purpose digital input/output pin.
1 I/O I2SRX_SDA I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification.
2 I/O SSEL1 SSP 1 Slave Select for SSP1.
3 O MAT2.0 Timer/Counter 2 Match output for Timer 2, channel 0.
80 P0.5/I2SRX_WS/TD2/CAP2.1 pinsel0
11:10
x
0 I/O P0.5 GPIO 0 General purpose digital input/output pin.
1 I/O I2SRX_WS I2S Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification.
2 O TD2 CAN 2 CAN2 transmitter output.
3 I CAP2.1 Timer/Counter 2 Capture input for Timer 2, channel 1.
81 P0.4/I2SRX_CLK/RD2/CAP2.0 pinsel0
9:8
x
0 I/O P0.4 GPIO 0 General purpose digital input/output pin.
1 I/O I2SRX_CLK I2S Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.
2 I RD2 CAN 2 CAN2 receiver input.
3 I CAP2.0 Timer/Counter 2 Capture input for Timer 2, channel 0.
82 P4.28/MAT2.0/TXD3 pinsel9
25:24
x
0 I/O P4.28 GPIO 4 General purpose digital input/output pin.
2 O MAT2.0 Timer/Counter 2 Match output for Timer 2, channel 0.
3 O TXD3 UART 3 Transmitter output for UART3.
83 VSS I VSS Main ground: 0 V reference.
84 VDD(DCDC)(3V3) I VDD(DCDC)(3V3) Main 3.3 V DC-to-DC converter supply voltage: This is the supply voltage for the on-chip DC-to-DC converter only.
85 P4.29/MAT2.1/RXD3 pinsel9
27:26
x
0 I/O P4.29 GPIO 4 General purpose digital input/output pin.
2 O MAT2.1 Timer/Counter 2 Match output for Timer 2, channel 1.
3 I RXD3 UART 3 Receiver input for UART3.
86 P1.17/ENET_MDIO pinsel3
3:2
x
0 I/O P1.17 GPIO 1 General purpose digital input/output pin.
1 I/O ENET_MDIO Ethernet Ethernet MIIM data input and output.
87 P1.16/ENET_MDC pinsel3
1:0
x
0 I/O P1.16 GPIO 1 General purpose digital input/output pin.
1 O ENET_MDC Ethernet Ethernet MIIM clock.
88 P1.15/ENET_REF_CLK pinsel2
31:30
x
0 I/O P1.15 GPIO 1 General purpose digital input/output pin.
1 I ENET_REF_CLK Ethernet Ethernet reference clock.
89 P1.14/ENET_RX_ER pinsel2
29:28
x
0 I/O P1.14 GPIO 1 General purpose digital input/output pin.
1 I ENET_RX_ER Ethernet Ethernet receive error.
90 P1.10/ENET_RXD1 pinsel2
21:20
x
0 I/O P1.10 GPIO 1 General purpose digital input/output pin.
1 I ENET_RXD1 Ethernet Ethernet receive data.
91 P1.9/ENET_RXD0 pinsel2
19:18
x
0 I/O P1.9 GPIO 1 General purpose digital input/output pin.
1 I ENET_RXD0 Ethernet Ethernet receive data.
92 P1.8/ENET_CRS pinsel2
17:16
x
0 I/O P1.8 GPIO 1 General purpose digital input/output pin.
1 I ENET_CRS Ethernet Ethernet carrier sense.
93 P1.4/ENET_TX_EN pinsel2
9:8
x
0 I/O P1.4 GPIO 1 General purpose digital input/output pin.
1 O ENET_TX_EN Ethernet Ethernet transmit data enable.
94 P1.1/ENET_TXD1 pinsel2
3:2
x
0 I/O P1.1 GPIO 1 General purpose digital input/output pin.
1 O ENET_TXD1 Ethernet Ethernet transmit data 0.
95 P1.0/ENET_TXD0 pinsel2
1:0
x
0 I/O P1.0 GPIO 1 General purpose digital input/output pin.
1 O ENET_TXD0 Ethernet Ethernet transmit data 0.
96 VDD(3V3) I VDD(3V3) Main 3.3 V supply voltage: This is the power supply voltage for the I/O ports.
97 VSS I VSS Main ground: 0 V reference.
98 P0.2/TXD0 pinsel0
5:4
x
0 I/O P0.2 GPIO 0 General purpose digital input/output pin.
1 O TXD0 UART 0 Transmitter output for UART0.
99 P0.3/RXD0 pinsel0
7:6
x
0 I/O P0.3 GPIO 0 General purpose digital input/output pin.
1 I RXD0 UART 0 Receiver input for UART0.
100 RTCK I/O RTCK JTAG JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as trace port after reset.


Function Blocks.

Function block ADC

Signal Pin I/O Description
VDDA 10 I analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC.
VREF 12 I ADC reference: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. Level on this pin is used as reference for ADC and DAC.
VSSA 11 I analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error.
AD0.0 9 I A/D converter 0, input 0.
AD0.1 8 I A/D converter 0, input 1.
AD0.2 7 I A/D converter 0, input 2.
AD0.3 6 I A/D converter 0, input 3.
AD0.4 21 I A/D converter 0, input 4.
AD0.5 20 I A/D converter 0, input 5.


Function block Battery

Signal Pin I/O Description
RTCX1 16 I Input to the RTC oscillator circuit.
RTCX2 18 O Output from the RTC oscillator circuit.
VBAT 19 I RTC pin power supply: 3.3 V on this pin supplies the power to the RTC peripheral.


Function block CAN

Generic Block Signals
Signal I/O Description
RDn I CANn receiver input.
TDn O CANn transmitter output.
Signals for CAN1
Signal Pins I/O Description
RD1 46 57 I CAN1 receiver input.
TD1 47 56 O CAN1 transmitter output.
Signals for CAN2
Signal Pins I/O Description
RD2 66 81 I CAN2 receiver input.
TD2 65 80 O CAN2 transmitter output.


Function block DAC

Signal Pin I/O Description
AOUT 6 O D/A converter output.


Function block EmbeddedTrace

EmbeddedTrace: see ETM in UserGuide (Chaper 31, P665).
Signal Pin I/O Description
TRACECLK 75 O TRACECLK -- Trace Clock.
TRACESYNC 69 O Trace Synchronization.
EXTIN0 64 I External Trigger Input.
PIPESTAT0 74 O Pipeline Status, bit 0.
PIPESTAT1 73 O Pipeline Status, bit 0.
PIPESTAT2 70 O Pipeline Status, bit 0.
TRACEPKT0 68 O Trace Packet, bit 0.
TRACEPKT1 67 O Trace Packet, bit 0.
TRACEPKT2 66 O Trace Packet, bit 0.
TRACEPKT3 65 O Trace Packet, bit 0.


Function block Ethernet

Signal Pin I/O Description
ENET_CRS 92 I Ethernet carrier sense.
ENET_MDC 87 O Ethernet MIIM clock.
ENET_MDIO 86 I/O Ethernet MIIM data input and output.
ENET_REF_CLK 88 I Ethernet reference clock.
ENET_RX_ER 89 I Ethernet receive error.
ENET_TX_EN 93 O Ethernet transmit data enable.
ENET_RXD0 91 I Ethernet receive data.
ENET_RXD1 90 I Ethernet receive data.
ENET_TXD0 95 O Ethernet transmit data 0.
ENET_TXD1 94 O Ethernet transmit data 0.


Function block ExtInt

Generic Block Signals
Signal I/O Description
!EINTn I External interrupt n input.
Signals for ExtInt0
Signal Pin I/O Description
!EINT0 53 I External interrupt 0 input.
Signals for ExtInt1
Signal Pin I/O Description
!EINT1 52 I External interrupt 1 input.
Signals for ExtInt2
Signal Pin I/O Description
!EINT2 51 I External interrupt 2 input.
Signals for ExtInt3
Signal Pin I/O Description
!EINT3 50 I External interrupt 3 input.


Function block GPIO

Generic Block Signals
Signal I/O Description
Pn.0 I/O General purpose digital input/output pin.
Signals for GPIO0
Signal Pin I/O Description
P0.0 46 I/O General purpose digital input/output pin.
P0.1 47 I/O General purpose digital input/output pin.
P0.2 98 I/O General purpose digital input/output pin.
P0.3 99 I/O General purpose digital input/output pin.
P0.4 81 I/O General purpose digital input/output pin.
P0.5 80 I/O General purpose digital input/output pin.
P0.6 79 I/O General purpose digital input/output pin.
P0.7 78 I/O General purpose digital input/output pin.
P0.8 77 I/O General purpose digital input/output pin.
P0.9 76 I/O General purpose digital input/output pin.
P0.10 48 I/O General purpose digital input/output pin.
P0.11 49 I/O General purpose digital input/output pin.
P0.15 62 I/O General purpose digital input/output pin.
P0.16 63 I/O General purpose digital input/output pin.
P0.17 61 I/O General purpose digital input/output pin.
P0.18 60 I/O General purpose digital input/output pin.
P0.19 59 I/O General purpose digital input/output pin.
P0.20 58 I/O General purpose digital input/output pin.
P0.21 57 I/O General purpose digital input/output pin.
P0.22 56 I/O General purpose digital input/output pin.
P0.23 9 I/O General purpose digital input/output pin.
P0.24 8 I/O General purpose digital input/output pin.
P0.25 7 I/O General purpose digital input/output pin.
P0.26 6 I/O General purpose digital input/output pin.
P0.27 25 I/O General purpose digital input/output pin. Output is open-drain.
P0.28 24 I/O General purpose digital input/output pin. Output is open-drain.
P0.29 29 I/O General purpose digital input/output pin.
P0.30 30 I/O General purpose digital input/output pin.
Signals for GPIO1
Signal Pin I/O Description
P1.0 95 I/O General purpose digital input/output pin.
P1.1 94 I/O General purpose digital input/output pin.
P1.4 93 I/O General purpose digital input/output pin.
P1.8 92 I/O General purpose digital input/output pin.
P1.9 91 I/O General purpose digital input/output pin.
P1.10 90 I/O General purpose digital input/output pin.
P1.14 89 I/O General purpose digital input/output pin.
P1.15 88 I/O General purpose digital input/output pin.
P1.16 87 I/O General purpose digital input/output pin.
P1.17 86 I/O General purpose digital input/output pin.
P1.18 32 I/O General purpose digital input/output pin.
P1.19 33 I/O General purpose digital input/output pin.
P1.20 34 I/O General purpose digital input/output pin.
P1.21 35 I/O General purpose digital input/output pin.
P1.22 36 I/O General purpose digital input/output pin.
P1.23 37 I/O General purpose digital input/output pin.
P1.24 38 I/O General purpose digital input/output pin.
P1.25 39 I/O General purpose digital input/output pin.
P1.26 40 I/O General purpose digital input/output pin.
P1.27 43 I/O General purpose digital input/output pin.
P1.28 44 I/O General purpose digital input/output pin.
P1.29 45 I/O General purpose digital input/output pin.
P1.30 21 I/O General purpose digital input/output pin.
P1.31 20 I/O General purpose digital input/output pin.
Signals for GPIO2
Signal Pin I/O Description
P2.0 75 I/O General purpose digital input/output pin.
P2.1 74 I/O General purpose digital input/output pin.
P2.2 73 I/O General purpose digital input/output pin.
P2.3 70 I/O General purpose digital input/output pin.
P2.4 69 I/O General purpose digital input/output pin.
P2.5 68 I/O General purpose digital input/output pin.
P2.6 67 I/O General purpose digital input/output pin.
P2.7 66 I/O General purpose digital input/output pin.
P2.8 65 I/O General purpose digital input/output pin.
P2.9 64 I/O General purpose digital input/output pin.
P2.10 53 I/O General purpose digital input/output pin. Note: LOW on this pin after reset forces on-chip bootloader to take over control.
P2.11 52 I/O General purpose digital input/output pin.
P2.12 51 I/O General purpose digital input/output pin.
P2.13 50 I/O General purpose digital input/output pin.
Signals for GPIO3
Signal Pin I/O Description
P3.25 27 I/O General purpose digital input/output pin.
P3.26 26 I/O General purpose digital input/output pin.
Signals for GPIO4
Signal Pin I/O Description
P4.28 82 I/O General purpose digital input/output pin.
P4.29 85 I/O General purpose digital input/output pin.


Function block I2C

Generic Block Signals
Signal I/O Description
SCLn I/O I2Cn clock input/output.
SDAn I/O I2Cn data input/output.
Signals for I2C0
Signal Pin I/O Description
SCL0 24 I/O I2C0 clock input/output. Open-drain output (for I2C-bus compliance).
SDA0 25 I/O I2C0 data input/output. Open-drain output (for I2C-bus compliance).
Signals for I2C1
Signal Pins I/O Description
SCL1 47 58 I/O I2C1 clock input/output. (this is not an open-drain pin).
SDA1 46 59 I/O I2C1 data input/output. (this is not an open-drain pin).
Signals for I2C2
Signal Pin I/O Description
SCL2 49 I/O I2C2 clock input/output. (this is not an open-drain pin).
SDA2 48 I/O I2C2 data input/output. (this is not an open-drain pin).


Function block I2S

Signal Pins I/O Description
I2SRX_CLK 9 81 I/O Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.
I2SRX_SDA 7 79 I/O Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification.
I2SRX_WS 8 80 I/O Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification.
I2STX_CLK 52 78 I/O Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.
I2STX_SDA 50 76 I/O Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification.
I2STX_WS 51 77 I/O Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification.


Function block JTAG

Signal Pin I/O Description
RTCK 100 I/O JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as trace port after reset.
TCK 5 I Test Clock for JTAG interface. This clock must be slower than 1/6 of the CPU clock (CCLK) for the JTAG interface to operate
TDI 2 I Test Data in for JTAG interface.
TDO 1 O Test Data out for JTAG interface.
TMS 3 I Test Mode Select for JTAG interface.
!TRST 4 I Test Reset for JTAG interface.


Function block Main

Signal Pins I/O Description
VSS 15 31 41 55 72 83 97 I ground: 0 V reference.
XTAL1 22 I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 23 O Output from the oscillator amplifier.
!RESET 17 I External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
!RSTOUT 14 O This is a 3.3 V pin. LOW on this pin indicates LPC23xx being in Reset state.
VDD(3V3) 28 54 71 96 I 3.3 V supply voltage: This is the power supply voltage for the I/O ports.
VDD(DCDC)(3V3) 13 42 84 I 3.3 V DC-to-DC converter supply voltage: This is the supply voltage for the on-chip DC-to-DC converter only.


Function block PWM

Signal Pins I/O Description
PCAP1.0 44 67 I Capture input for PWM1, channel 0.
PCAP1.1 45 I Capture input for PWM1, channel 1.
PWM1.1 32 75 O Pulse Width Modulator 1, channel 1 output.
PWM1.2 27 34 74 O Pulse Width Modulator 1, channel 2 output.
PWM1.3 26 35 73 O Pulse Width Modulator 1, channel 3 output.
PWM1.4 37 70 O Pulse Width Modulator 1, channel 4 output.
PWM1.5 38 69 O Pulse Width Modulator 1, channel 5 output.
PWM1.6 40 68 O Pulse Width Modulator 1, channel 6 output.


Function block SPI

Signal Pin I/O Description
MISO 61 I/O Master In Slave Out for SPI.
MOSI 60 I/O Master Out Slave In for SPI.
SCK 62 I/O Serial clock for SPI.
SSEL 63 I/O Slave Select for SPI.


Function block SSP

Generic Block Signals
Signal I/O Description
MISOn I/O Master In Slave Out for SSPn.
MOSIn I/O Master Out Slave In for SSPn.
SCKn I/O Serial clock for SSPn.
SSELn I/O Slave Select for SSPn.
Signals for SSP0
Signal Pins I/O Description
MISO0 37 61 I/O Master In Slave Out for SSP0.
MOSI0 38 60 I/O Master Out Slave In for SSP0.
SCK0 34 62 I/O Serial clock for SSP0.
SSEL0 35 63 I/O Slave Select for SSP0.
Signals for SSP1
Signal Pins I/O Description
MISO1 77 I/O Master In Slave Out for SSP1.
MOSI1 76 I/O Master Out Slave In for SSP1.
SCK1 20 78 I/O Serial clock for SSP1.
SSEL1 79 I/O Slave Select for SSP1.


Function block Timer/Counter

Generic Block Signals
Signal I/O Description
CAPn.0 I Capture input for Timer n, channel m.
MATn.0 O Match output for Timer n, channel m.
Signals for Timer/Counter0
Signal Pins I/O Description
CAP0.0 40 I Capture input for Timer 0, channel 0.
CAP0.1 43 I Capture input for Timer 0, channel 1.
MAT0.0 27 44 O Match output for Timer 0, channel 0.
MAT0.1 26 45 O Match output for Timer 0, channel 1.
Signals for Timer/Counter1
Signal Pin I/O Description
CAP1.0 32 I Capture input for Timer 1, channel 0.
CAP1.1 33 I Capture input for Timer 1, channel 1.
MAT1.0 36 O Match output for Timer 1, channel 0.
MAT1.1 39 O Match output for Timer 1, channel 1.
Signals for Timer/Counter2
Signal Pins I/O Description
CAP2.0 81 I Capture input for Timer 2, channel 0.
CAP2.1 80 I Capture input for Timer 2, channel 1.
MAT2.0 79 82 O Match output for Timer 2, channel 0.
MAT2.1 78 85 O Match output for Timer 2, channel 1.
MAT2.2 77 O Match output for Timer 2, channel 2.
MAT2.3 76 O Match output for Timer 2, channel 3.
Signals for Timer/Counter3
Signal Pin I/O Description
CAP3.0 9 I Capture input for Timer 3, channel 0.
CAP3.1 8 I Capture input for Timer 3, channel 1.
MAT3.0 48 O Match output for Timer 3, channel 0.
MAT3.1 49 O Match output for Timer 3, channel 1.


Function block UART

Remark: UART0 can be used for ISP after reset. See User Manual Chapter 29: LPC23XX Flash memory programming firmware.
Generic Block Signals
Signal I/O Description
CTSn I Clear to Send input for UARTn.
DCDn I Data Carrier Detect input for UARTn.
DSRn I Data Set Ready input for UARTn.
DTRn O Data Terminal Ready output for UARTn.
RIn I Ring Indicator input for UARTn.
RTSn O Request to Send output for UARTn.
RXDn I Receiver input for UARTn.
TXDn O Transmitter output for UARTn.
Signals for UART0
Signal Pin I/O Description
RXD0 99 I Receiver input for UART0.
TXD0 98 O Transmitter output for UART0.
Signals for UART1
Signal Pins I/O Description
CTS1 61 73 I Clear to Send input for UART1.
DCD1 60 70 I Data Carrier Detect input for UART1.
DSR1 59 69 I Data Set Ready input for UART1.
DTR1 58 68 O Data Terminal Ready output for UART1.
RI1 57 67 I Ring Indicator input for UART1.
RTS1 56 66 O Request to Send output for UART1.
RXD1 63 74 I Receiver input for UART1.
TXD1 62 75 O Transmitter output for UART1.
Signals for UART2
Signal Pins I/O Description
RXD2 49 64 I Receiver input for UART2.
TXD2 48 65 O Transmitter output for UART2.
Signals for UART3
Signal Pins I/O Description
RXD3 6 47 85 I Receiver input for UART3.
TXD3 7 46 82 O Transmitter output for UART3.


Function block USB

Signal Pin I/O Description
USB_CONNECT 64 O Signal used to switch an external 1.5 kOhm resistor under software control. Used with the SoftConnect USB feature.
USB_D- 30 I/O USB bidirectional D- line.
USB_D+ 29 I/O USB bidirectional D+ line.
USB_UP_LED 32 O USB GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend.
VBUS 21 I Monitors the presence of USB bus power.Note: This signal must be HIGH for USB reset to occur.



pinsel registers.

pinsel0 pinsel1 pinsel2 pinsel3 pinsel4
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
pinsel5 pinsel6 pinsel7 pinsel8 pinsel9
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000


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